Patent
1981-08-04
1984-05-29
Larkins, William D.
357 34, 357 50, 357 58, 357 65, H01L 2350, H01L 2352
Patent
active
044518447
ABSTRACT:
A semiconductor device comprising a semiconductor substrate of an N conductivity type; an insulation layer of a predetermined pattern for selectively covering the substrate; a first region of a P conductivity type formed in that area of the substrate which is surrounded by the insulation layer; a second region of the P.sup.+ conductivity type having a high impurity concentration and formed in the first region; a third region of the N conductivity type formed in the first region; a polycrystalline silicon layer formed on the major surface of the substrate, said polycrystalline silicon layer comprising a first portion of the P conductivity type contacting the second region, a second portion of the N conductivity type contacting the third region and a third portion contacting the first region, said first and second portions constituting first and second contacting electrodes, respectively, and the third portion having a predetermined impurity concentration and constituting a separation portion for insulating the first and second portions from each other.
REFERENCES:
patent: 3728590 (1973-04-01), Kim et al.
patent: 4031608 (1977-06-01), Togei et al.
patent: 4074304 (1978-02-01), Shiba
patent: 4161745 (1979-07-01), Slob
Komatsu Shigeru
Nakamura Michio
Larkins William D.
Tokyo Shibaura Denki Kabushiki Kaisha
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