Processor having a bus interconnect which is dynamically reconfi

Details Processor having a bus interconnect which is dynamically reconfi Processor having a bus interconnect which is dynamically reconfi

1996-05-17

1998-06-23

Auve, Glenn A.

395306, G06F 1300

Patent

active

057713626

ABSTRACT:
A processor employing a dynamically configurable bus interconnect is provided. The interconnect routes data between functional units and memories included within the processor in response to an instruction field. As opposed to a particular hard-wired interconnect, the dynamically variable interconnect may be modified to form an optimum interconnect for the particular algorithm being executed. Still further, the interconnect may be modified between several configurations during the execution of the algorithm, as often as each clock cycle. Because an instruction field is used to directly specify the configuration of the interconnect during execution of that instruction, control over the interconnect is afforded to the programmer writing the code which implements a particular algorithm.

REFERENCES:
Corporaal, H. et al., "Move: A Framework for High-Performance Processor Design," Institute of Electrical and Electronics Engineers, Proceedings of the Supercomputing Conference, Albuquerque, Nov. 18-22, 1991, XP000337525, pp. 692-701.
International Search Report for PCT/US 97/01044.

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