Intra-gate offset high voltage thin film transistor with misalig

Details Intra-gate offset high voltage thin film transistor with misalig Intra-gate offset high voltage thin film transistor with misalig

1989-11-02

1990-07-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 57, 437 50, 437229, 357 233, 357 237, H01L 21265

Patent

active

049450670

ABSTRACT:
A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes in the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantial alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic regions thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower depant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.

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