Parallel processing method having arithmetical conditions code b

Details Parallel processing method having arithmetical conditions code b Parallel processing method having arithmetical conditions code b

1996-07-10

1998-06-23

Kim, Kenneth S.

395708, 395562, 395581, 39580023, 395391, G06F 945

Patent

active

057708940

ABSTRACT:
A computer implemented method performed by a processor having multiple functional units avoids branches in decision support codes by doing arithmetic instructions incorporating condition codes generated by compare instructions. The method comprising the steps of analyzing operations in code to be performed by said processors to identify branch operations, substituting for identified branch operations arithmetic condition codes, decoding and dispatching multiple instructions in one processor cycle, and executing multiple functions in parallel per cycle using each of the functional units of said processor.

REFERENCES:
patent: 5471593 (1995-11-01), Branigin
patent: 5596732 (1997-01-01), Hosoi

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