Patent
1994-10-05
1997-01-14
Lall, Parshotam S.
395307, 395482, G06F 1340
Patent
active
055948774
ABSTRACT:
The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. The use of a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.
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Lentz Derek J.
Tang Cheng-Long
Lall Parshotam S.
Seiko Epson Corporation
Vu Viet
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