Patent
1996-02-28
1997-05-13
Harvey, Jack B.
395348, G06F 1300
Patent
active
056301480
ABSTRACT:
A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.
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patent: 5230074 (1993-07-01), Canova, Jr. et al.
patent: 5292341 (1994-03-01), Snell
Harvey Jack B.
Intel Corporation
Travis John
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