Dynamic processor performance and power management in a computer

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Details

395348, G06F 1300

Patent

active

056301480

ABSTRACT:
A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.

REFERENCES:
patent: 4775935 (1988-10-01), Yourick
patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5142684 (1992-08-01), Perry et al.
patent: 5230074 (1993-07-01), Canova, Jr. et al.
patent: 5292341 (1994-03-01), Snell

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