Write combining buffer for sequentially addressed partial line o

Details Write combining buffer for sequentially addressed partial line o Write combining buffer for sequentially addressed partial line o

1995-05-25

1997-05-13

Ellis, Richard L.

G06F 506

Patent

active

056300751

ABSTRACT:
A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for combining data of at least two write commands into a single data set, wherein the combined data set is transmitted over the bus in one clock cycle rather than two or more clock cycles. Thereby, buss traffic is minimized. The write combining buffer is comprised of a single line having a 32-byte data portion, a tag portion, and a validity portion. The tag entry specifies the address corresponding to the data currently stored in the data portion. There is one valid bit corresponding to each byte of the data portion which specifies whether that byte currently contains useful data. So long as subsequent write operations to the write combining buffer result in hits, the data is written to the buffer's data portion. But when a miss occurs, the line is reallocated, and the old data is written to the main memory. Thereupon, the valid bits are cleared, and the new data and its address are written to the write combining buffer.

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Popescu, et al., "The Metaflow Architecture," IEEE Micro, pp. 10-13 and 63-73, Jun. 1991.

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