Fault-tolerant computer system capable of preventing acquisition

Details Fault-tolerant computer system capable of preventing acquisition Fault-tolerant computer system capable of preventing acquisition

1995-03-22

1997-05-13

Beausoliel, Jr., Robert W.

39518209, 39518501, G06F 1100

Patent

active

056300530

ABSTRACT:
In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths. The n-th processor comprises an n-th central processing unit (CPU) for managing the whole of the (n-1)-th processor, an n-th failure detecting circuit for always monitoring an operation state in the (n-1)-th processor, and an n-th input/output information transmission path acquisition control circuit for directing control operation for the input/output information transmission path control device.

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