Patent
1995-01-17
1997-05-13
Downs, Robert W.
395 24, G06F 1518
Patent
active
056300247
ABSTRACT:
A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is judged that the obtained summation value reached to the saturation region.
REFERENCES:
patent: 4943931 (1990-07-01), Allen
patent: 5131073 (1992-07-01), Furuta et al.
patent: 5166539 (1992-11-01), Uchimura et al.
patent: 5208900 (1993-05-01), Gardner
patent: 5276773 (1994-01-01), Knauer et al.
patent: 5324991 (1994-06-01), Furuta et al.
patent: 5350953 (1994-09-01), Swenson et al.
patent: 5353383 (1994-10-01), Uchimura et al.
patent: 5384896 (1995-01-01), Sakaue et al.
patent: 5408585 (1995-04-01), Burel
patent: 5440671 (1995-08-01), Shiratani et al.
patent: 5450528 (1995-09-01), Chung et al.
patent: 5467429 (1995-11-01), Uchimura et al.
patent: 5473730 (1995-12-01), Simard
patent: 5473731 (1995-12-01), Seligson
patent: 5481646 (1996-01-01), Furuta et al.
patent: 5490164 (1996-02-01), Shimura
patent: 5519813 (1996-05-01), Furuta et al.
IEEE Journal of Solid-State Circuit, vol. 27, No. 12, 1 Dec. 1992, pp. 1862-1867, XP 000329038, Kuniharu Uchimura et al., "A High-Speed Digital Neural Network Chip with Low-Power Chain-Reaction Architecture".
Neural Information Processing Systems, Editor D. Anderson, American Institute of Physics, 1987 Denver, pp. 573-583, Murray "Bit-Serial Neural Networks", p. 576, line 8, p. 578, line 13, Figures 3-5.
Aihara Kimihisa
Uchimura Kuniharu
Downs Robert W.
Nippon Telegraph and Telephone Corporation
Smith Jeffrey
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