Test mode setting circuit of test circuit for semiconductor memo

Details Test mode setting circuit of test circuit for semiconductor memo Test mode setting circuit of test circuit for semiconductor memo

1996-06-25

1997-05-13

Canney, Vincent P.

Excavating

371 28, G01R 3128

Patent

active

056299443

ABSTRACT:
A test mode setting circuit includes a high voltage detection circuit, an uppermost row address buffer and a row address buffer control circuit for the uppermost row address buffer. When a high voltage is supplied to a common input terminal for the test mode setting, the uppermost row address buffer receives through the common input terminal an uppermost address signal, and provides the uppermost address signal as an uppermost internal row address signal. The row address buffer control circuit operates such that, when an upper stage transistor in stacked two N-channel MOS transistors of the uppermost row address buffer becomes conductive through the high voltage, an internal control signal for the uppermost row address buffer is supplied to a lower stage transistor connected to a ground thus causing the lower stage transistor to become a non-conductive state whereby a voltage across the gate and source electrodes and a voltage across the gate and drain electrodes of the upper stage transistor are rendered to be a level lower than the high voltage. This enables the relaxing of the high electric field applied to the gate electrode and the reducing of the likelihood of the destruction of the gate oxide film.

REFERENCES:
patent: 5469444 (1995-11-01), Endoh et al.
patent: 5521868 (1996-05-01), Nobukata
patent: 5544175 (1996-08-01), Posse

Affiliated with

Also associated with

Rating

Test mode setting circuit of test circuit for semiconductor memo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test mode setting circuit of test circuit for semiconductor memo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test mode setting circuit of test circuit for semiconductor memo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1391444