Integrated circuit memory with double bitline low special test m

Details Integrated circuit memory with double bitline low special test m Integrated circuit memory with double bitline low special test m

1994-05-31

1997-05-13

Beausoliel, Jr., Robert W.

Excavating

365201, G11C 2900

Patent

active

056299435

ABSTRACT:
Circuitry for performing a special test of an integrated memory circuit is disclosed, where the special test requires driving of both bitlines associated with a column of memory cells to a selected logic level, such as ground. The special test is performed in a mode different from normal operation of the memory, and is useful in performing a write disturb test, and in performing stress tests of memory elements such as pass transistors in static random access memory cells. The special test is performed by generating an internal signal selecting the placement of both bitlines in one or more bitline pairs to the selected logic level. Circuitry is also disclosed which uses the output enable terminal, in the special test mode, for controlling the driving of both bitlines to the selected logic level, as the output enable terminal otherwise has no required function in this special test mode.

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patent: 5347843 (1994-09-01), Torimaru

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