Method for timing-directed circuit optimizations

Details Method for timing-directed circuit optimizations Method for timing-directed circuit optimizations

1994-09-12

1997-05-13

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 371 223, 371 221, G06F 1500

Patent

active

056298595

ABSTRACT:
Shown is a method of optimizing the performance of a logic circuit. The circuit is represented as a set of vertices, with each element output being represented as a vertex whose element is selected for local optimization on a depth first traversal basis. As each element is optimized, its path length is calculated by partial path lengths, which are known to be either valid or invalid as a result of prior local optimizations. Specifically, invalid path lengths to the associated vertex from circuit inputs are re-computed and added to valid path lengths from the associated vertex to a circuit output.

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