Static information storage and retrieval – Plural shift register memory devices
Patent
1985-12-20
1987-09-15
Popek, Joseph A.
Static information storage and retrieval
Plural shift register memory devices
377 28, 377 66, G11C 1900
Patent
active
046944265
ABSTRACT:
A FIFO status circuit suitable to detect the full or empty status of a RAM based FIFO which is asynchronously addressable by write and read access signals. The circuit detects whether the preceding addressing of the FIFO was a read or a write operation to determine whether the FIFO is empty or full. In one form, the trailing edges of the FIFO write and read signals trigger respective pulse generators. Short duration matched pulses drive the corresponding set and reset inputs of a flip-flop. The out Q and Q outputs from the flip-flop are coupled individually to a pair of AND gates. Each AND gate is also driven by a FIFO equal signal, a signal which indicates that both the read pointer and write pointer of the FIFO memory are directed to the same address. Because the FIFO equal signal is stable before the pulses reach the flip-flop, it serves to mask metastable conditions which may arise in the flip-flop. The flip-flop defines whether the previous operation was a read or write, and as such when combined by the AND gates defines whether the matching of the FIFO address pointers corresponds to a memory full or empty state.
REFERENCES:
patent: 3953838 (1976-04-01), Gilberg et al.
patent: 4156288 (1979-05-01), Spandorfer
patent: 4459681 (1984-07-01), Ohtsuka
Hawk Jr. Wilbert
NCR Corporation
Popek Joseph A.
Salys Casimer K.
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