Microprocessor system having a multiplexed address/data bus whic

Details Microprocessor system having a multiplexed address/data bus whic Microprocessor system having a multiplexed address/data bus whic

1985-10-10

1987-09-15

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1300

Patent

active

046943943

ABSTRACT:
A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.

REFERENCES:
patent: 4349870 (1982-09-01), Shaw et al.
patent: 4433413 (1984-02-01), Fasang

Affiliated with

Also associated with

Rating

Microprocessor system having a multiplexed address/data bus whic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor system having a multiplexed address/data bus whic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor system having a multiplexed address/data bus whic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1389567