Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1995-11-02
1997-05-13
Gaffin, Jeffrey A.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341155, 341156, H03M 134
Patent
active
056297009
ABSTRACT:
An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.
REFERENCES:
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IEEE 1991 Custom Integrated Circuits Conference, pp. 26.4.1-26.4.4, Stephen H. Lewis, et al., "A Pipelined 9-Stage Video-Rate Analog-To-Digital Converter".
IEEE 1992 Custom Integrated Circuits Conference, pp. 16.7.1-16.7.4, Michio Yotsuyanagi, et al., "A 10BIT 50Msample/sec Pipelined CMOS A/D Converter with S/H".
Analog Devices, Design-In Reference Manual, Part Numbers AD875 and 873 Aug. 1994.
Ito Masao
Kumamoto Toshio
Matsumoto Osamu
Miki Takahiro
Okuda Takashi
Gaffin Jeffrey A.
Mitsubishi Denki & Kabushiki Kaisha
Vick Jason H.
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