Register scorboarding on a microprocessor chip

Details Register scorboarding on a microprocessor chip Register scorboarding on a microprocessor chip

1986-11-26

1990-01-02

Shaw, Gareth D.

Boots, shoes, and leggings

364231, 3642328, 364258, 3642599, 364247, 3642624, 3642628, G06F 918

Patent

active

048917532

ABSTRACT:
When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.

REFERENCES:
patent: 4156278 (1979-05-01), Wilhite
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4325120 (1982-04-01), Colley et al.
patent: 4472787 (1984-09-01), Busby
patent: 4507728 (1985-03-01), Sakamoto et al.
patent: 4589064 (1986-05-01), Chiba et al.
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4680730 (1987-07-01), Omoda et al.

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