Lightly-doped drain transistor structure in contactless DRAM cel

Details Lightly-doped drain transistor structure in contactless DRAM cel Lightly-doped drain transistor structure in contactless DRAM cel

1986-08-22

1990-01-02

Mintel, William

357 59, 357 45, 357 90, 357 53, H01L 2978

Patent

active

048917478

ABSTRACT:
A dynamic RAM cell of the contactless type with a buried N+ source/drain region is constructed by the metal-gate non-self-aligned technique. A lightly-doped drain is provided by employing both arsenic and phosphorus in the buried N+ region. The effects of impact ionization are thus minimized, and a high density cell array is provided.

REFERENCES:
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patent: 4290186 (1981-09-01), Klein et al.
patent: 4455566 (1984-06-01), Sakurai
patent: 4489338 (1984-12-01), Voncken
patent: 4597000 (1986-06-01), Adam
patent: 4622570 (1986-11-01), Taguchi
Walker, "Process for Making a Push Plate RAM Cell, " IBM Technical Disclosure Bulletin, vol. 26, No. 10A, Mar. 1984, pp. 4931-4933.
Sodini et al., "Enhanced Capacitor for One-Transistor Memory Cell," IEEE Transactions on Electron Devices, Oct. 1976, pp. 1187-1189.

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