Single supply ECL to CMOS converter

Details Single supply ECL to CMOS converter Single supply ECL to CMOS converter

1988-12-20

1990-01-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072961, 307356, 307358, 307455, 323314, H03K 19092, H03K 19086, H03K 1710, H03K 3013

Patent

active

048915351

ABSTRACT:
An ECL to CMOS converter having a diferential ECL clock input and an ECL data input is provided. A reference voltage is generated by averaging the level shifted differential ECL clock signals using a voltage divider. This reference voltage and the level shifted ECL data input are compared by a CMOS comparator to provide a CMOS data output. The level shifters, comparators, and the voltage divider are integrated in a standard VLSI CMOS process that enables the resultant integrated circuit to operate from a single supply voltage.

REFERENCES:
patent: 4539551 (1985-09-01), Fujita et al.
patent: 4700087 (1987-10-01), Stroberger
patent: 4727265 (1988-02-01), Nanbu et al.
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4810908 (1989-03-01), Suzuki et al.
patent: 4849659 (1989-07-01), West
"Fast CMOS ECL Receivers With 100-mv Worst-Case Sensitivity" (Chappell et al.), IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988.
"A 140 Mbit/s CMOS LSI Framer Chip for a Broad-Bank ISDN Local Access System" (Author: Chao et al.), IEEE Journal of Solid State Circuits, vol. 23, No. 1 (2/88).

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