Method for processor modeling in code generation and instruction

Details Method for processor modeling in code generation and instruction Method for processor modeling in code generation and instruction

1995-05-15

1999-06-29

Louis-Jacques, Jacques H.

395702, 395704, 395705, 395564, G06F 300

Patent

active

059180358

ABSTRACT:
A method of modeling a programmable processor is particularly adapted for use in an automatic retargetable code generator and instruction set simulator. The method represents the processor as a single graph with vertices and edges. The graph includes the instruction set of the processor and includes information about the hardware of the processor. The graph is linked to tools and libraries required to program and simulate the processor.

REFERENCES:
patent: 5513122 (1996-04-01), Cheng et al
patent: 5522063 (1996-05-01), Ashar et al.
patent: 5568396 (1996-10-01), Banji et al.
patent: 5568636 (1996-10-01), Koford
C.G. Bell and A. Newell, Computer Structures: Readings and Examples, McGraw-Hill, New York, 1971, pp. 30-33.
R. Steven Glanville, et al., "A New Method for Compiler Code Generation," Proceedings of the 5th Annual ACM Symposium on Principals of Programming Languages, 1978, pp. 231-240.
David Landskov, et al., "Local Microcode Compaction Techniques," Computing Surveys, vol. 12, No. 3, Sep. 1980, pp. 261-294.
Robert A. Mueller, et al., "Flow Graph Machine Models in Microcode Synthesis," 16th Annual Microprogramming Workshop (Micro 16), ACM, 1983, pp. 159-167.
Alfred V. Aho, et al., "Code Generation Using Tree Matching and Dynamic Processing," ACM Transactions on Programming Languages and Systems, vol. 11, No. 4, Oct. 1986, pp. 491-516.
Lothar Nowak, et al., "Verification of Hardware Descriptions by Retargetable Code Generation," 26th ACM/IEEE Design Automation Conference, Paper 28.2, 1989, pp. 441-447.
Jack W. Davidson, et al., "The Design and Application of a Retargetable Peephole Optimizer," ACM Transactions on Programming Languages and Systems, vol. 2, No. 2, Apr. 1990, pp. 191-202.
David Gordan Bradlee, "Marion Code Generation Construction System," Chapter 3 of Ph.D. Thesis: Retargetable Instruction Scheduling for Pipelined Processor, University of Washington, 1991, pp. 13-24.
A. Fauth, et al., "Automated Generation of DSP Program Development Tools Using a Machine Language Description Formalism," Proceedings of IEEE, ICASSP '93, IEEE, Minneapolis, 1993, four pages.
Johan Van Praet, et al., "Instruction Set Definition and Instruction Selection for ASIPs," Symposium on High Level Synthesis, Ontario, Canada, May 18-20, 1994, pp. 11-16.
Pierre G. Paulin, et al., "DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective," Journal of VLSI Signal Processing, vol. 9, 1995, pp. 23-47.
A. Fauth, et al., "Describing Instruction Set Processors Using nML," Proceedings of European Design & Test Conference '95, Paris, France, Mar. 6-9, 1995, five pages.

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