Computer architecture capable of concurrent issuance and executi

Details Computer architecture capable of concurrent issuance and executi Computer architecture capable of concurrent issuance and executi

1997-10-28

1999-06-29

Coleman, Eric

395392, G06F 938

Patent

active

059180323

ABSTRACT:
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

REFERENCES:
patent: 5560032 (1996-09-01), Nguyen
patent: 5651124 (1997-07-01), Shen
patent: 5832292 (1998-11-01), Nguyen

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