Method of fabricating a self-aligned trench isolation scheme for

Details Method of fabricating a self-aligned trench isolation scheme for Method of fabricating a self-aligned trench isolation scheme for

1995-04-13

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437 67, 437984, H01L 218247

Patent

active

055061605

ABSTRACT:
The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme allows bit line to bit line spacing to be scaled to 0.6 .mu.m and below without compromising either data retention or memory performance characteristics. A new poly stack self-aligned etch scheme is also provided to scale the word line spacing to 0.6 .mu.m and below and, thus, allow a 64 Mbit EPROM array to be realized.

REFERENCES:
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patent: 5240870 (1993-08-01), Bergemont
patent: 5246874 (1993-09-01), Bergemont
"Sidewall Channel-Stop Doping For Deep-Trench Isolation of FET Devices", IBM Technical Disclosure Bulletin, vol. 27, No. 10A, Mar. 1985, pp. 5501-5504.
Hisamune et al., "A 3.6 .mu.m.sup.2 Memory cell structure for 16MB EPROMS", IEEE, 1989, pp. 25.2.1-25.2.4.
Boaz Eitan et al., "Alternate Metal Virtual Ground (AMG)--A New Scaling Concept for Very High-Density EPROMS"; IEEE 1991, vol. 12, No. 8, Aug. 1991, pp. 450-452.
R. Kazerounian et al., "Alternate Metal Virtual Ground EPROM Array Implemented in a 0.8 .mu.m Process For Very High Density Applications", IEDM 1991, pp. 311-314.
Graham R. Wolstenholme et al., "A Novel Isolation Scheme for Implementation in Very High Density AMG EPROM and Flash EEPROM Arrays".

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