Fault tolerant memory system

Details Fault tolerant memory system Fault tolerant memory system

1998-01-05

1999-06-29

Chung, Phung M.

Excavating

371 3701, 371 3702, 371 30, H03M 1300

Patent

active

059178388

ABSTRACT:
A fault tolerant memory system having a triple bit error correction and quadruple bit error detection capability is disclosed using control logic coupled to multiple decoders each having single bit error correction/double bit error detection capabilities. The memory system can also be provided with a sparing system which provides an additional memory device to circumvent failures in individual memory devices. The memory system is suited for severe environments such as computing systems operating in outer space.

REFERENCES:
patent: 4317201 (1982-02-01), Sedalis
patent: 4584682 (1986-04-01), Shah et al.
"PCM Telecommand Standard", European Space Research & Agency, Apr. 1978, pp. 1-48, Noordwijk, The Netherlands.

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