Register bank bit lines

Details Register bank bit lines Register bank bit lines

1997-11-03

1999-06-29

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365227, 36518525, G11C 800

Patent

active

059177713

ABSTRACT:
A data processing apparatus is provided comprising a processor core for performing processing operations, and a register bank comprising a plurality of registers for storing data values used by the processor core, the register bank having first and second portions such that in preferred embodiments the first portion of the register bank may be arranged to include the more frequently accessed registers. Each register in the register bank comprises a plurality of memory cells for storing data bits, and the register bank has a bit line associated with corresponding memory cells from a number of said registers, each memory cell being arranged, upon receipt of a command, to selectively alter the associated bit line from a first state to a second state dependent on the data bit stored in that memory cell.
In accordance with the present invention, a separation circuit is provided to separate the bit line into first and second parts, the first part being associated with memory cells of registers in the first portion of the register bank and being coupled to an output of the register bank, and the second part being associated with memory cells of registers in the second portion of the register bank. The separation circuit is responsive to a memory cell of a register in the second portion of the register bank altering the second part of the bit line to said second state, to cause the first part of the bit line to be altered to said second state, whereas if a memory cell of a register in the first portion of the register bank alters the first part of the bit line to said second state, the separation circuit is arranged to maintain the second part of the bit line in the first state.
By this approach, the power consumption required to operate the register bank is reduced since when reading the registers in the first portion of the register bank, only part of the bit line has to be discharged. If the first portion of the register bank is arranged to include the most frequently accessed registers, then significant power savings can be realized.

REFERENCES:
patent: 4810910 (1989-03-01), Schoellikopf et al.
patent: 5748551 (1998-05-01), Ryan et al.
patent: 5815457 (1998-09-01), Pascucci
patent: 5822268 (1998-10-01), Kirihata
patent: 5841727 (1998-11-01), Iwanari et al.

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