Semiconductor memory having hierarchical bit line architecture w

Details Semiconductor memory having hierarchical bit line architecture w Semiconductor memory having hierarchical bit line architecture w

1997-12-18

1999-06-29

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365 51, 365205, 365207, G11C 506

Patent

active

059177446

ABSTRACT:
Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SA.sub.i), at least one pair of master bitlines (MBL.sub.i, MBL.sub.i ) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL.sub.1i, LBL.sub.1i , LBL.sub.2i, LBL.sub.2i ), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.

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