Boots – shoes – and leggings
Patent
1997-02-27
1999-06-29
Mai, Tan V.
Boots, shoes, and leggings
3647462, G06G 700, G06F 700
Patent
active
059177420
ABSTRACT:
A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for the simultaneous input of the plurality of data, a mechanism for conducting a batch addition operation with respect to all the bits of the plurality of data, and for generating an analog or multi-valued signal having a linear relationship with the results of this addition and a mechanism for converting the analog or multi-valued signal to a digital signal. The plurality of data comprise bit data signals, and 4 or more of these are subjected to batch addition. A plurality of bit groups including a plurality of connected bits are also subjected to batch addition.
REFERENCES:
patent: 4140920 (1979-02-01), Dao et al.
patent: 4390962 (1983-06-01), Current
Imai Makoto
Kotani Koji
Ohmi Tadahiro
Shibata Tadashi
Knuth Randall J.
Mai Tan V.
Shibata Tadashi
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