Parallel decimator method and apparatus

Details Parallel decimator method and apparatus Parallel decimator method and apparatus

1996-09-24

1999-06-29

Grant, William

Boots, shoes, and leggings

36473601, 364768, 364724011, 364723, 364825, G06F 1717, G06F 738, G06G 702

Patent

active

059177349

ABSTRACT:
A decimation device has a sampler, a memory and an adder in the decimation stage. The sampler and the adder from a partial sample for storage in the memory at a sample time. At a next sample time the sum of a current sample and the partial sample is output from the decimation stage. The partial sample is formed by adding the first sample to a value equal to twice a second sample obtained after the first sample.

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Karema et al, "A Filter Processor for Interpolation and Decimation", Proceedings of the Custom Integ. Circuits Conf., May 3-6, 1992, pp. 19-2.1-19.2.4.

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