High impedance technique for testing interconnections in digital

Details High impedance technique for testing interconnections in digital High impedance technique for testing interconnections in digital

Filed on

1993-06-17

Date issued

1995-12-05

Examiner

Voeltz, Emanuel T.

Patent Class

Excavating

Other Related Categories

G01R 3128, H03K 1900

Type

Patent

Status

active

Patent number

054736170

Description

ABSTRACT:
A boundary scan transmit cell having a three-state output buffer and logic circuitry for controlling the enabled or disabled state of the three-state buffer as a function of a scan input; and a boundary scan receive cell having an input buffer and a holding circuit for changing the input of the buffer to a predetermined logical state if such input is open or at a high impedance. Also disclosed is a bidirectional boundary scan cell that includes the functions of the disclosed boundary scan transmit and receive scan cells.

REFERENCES:
patent: 5115191 (1992-05-01), Yoshimori
patent: 5202625 (1993-04-01), Farwell
patent: 5285119 (1994-02-01), Takahashi

Affiliated with

Also associated with

Rating

High impedance technique for testing interconnections in digital does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High impedance technique for testing interconnections in digital, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High impedance technique for testing interconnections in digital will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1379633