Multiplex communications – Wide area network – Packet switching
Patent
1995-12-28
1999-04-06
Dung, Dinh C.
Multiplex communications
Wide area network
Packet switching
39580029, 370392, G06F 15173
Patent
active
058929231
ABSTRACT:
A parallel computer using a simply structured network which allows loads on message-transferring routes to be as equally distributed as possible and which eases possible conflict between different types of messages being transferred. Given a message to be transmitted, each processor (PE) on the network references a property setup table to determine property information depending on the message type and places the information into the message. For example, a route bit RB as the property information is set to "0" or "1" depending on whether the message is originated by the sending PE or is a message acknowledging the receipt of another message. According to the RB bit in the received message, a route instruction circuit in each exchange switch (EX) references a route instruction table to determine the message destination that depends on the receiving PE number designated by the message. Each EX has a plurality of virtual channel circuits. Each virtual channel circuit has a plurality of buffers assigned beforehand to different values of the RB bit within the message. The received message is placed into the buffer corresponding to the RB bit value of the message, whereby conflict between messages is minimized.
REFERENCES:
patent: 5222085 (1993-06-01), Newman
patent: 5583990 (1996-12-01), Birrittella et al.
H. Park et al. "WICI: An Efficient Switching Scheme for Large Scalable Networks", Parallel and Distriubted Processing, 1994 proceeding, pp. 385-392. CD. IEE/IEEE IHS Electronic Lib.
F.C.M. Lau et al. "Propagating Buffer: A new approach to deadlock freedom in store-and-forward networks", Parallel and Distriubted Processing, 1991 proceeding, pp.804-807. CD. IEE/IEEE IHS Electronic Lib.
Awerbuch et al. "On Buffer-Economical Store-and-Forward Deadlock Prevention", IEEE publication pp.4D.1.1 -4D.1.5. CD. IEE/IEEE IHS Electronic Lib., 1991.
Shen et al. "The B-&-E Model for Adaptive Wormhole Routing", Parallel and Distributed Processing, 1993, pp. 170-173. CD. Proquest IEEE/IEE Publications Ondisc.
Information Processing Society of Japan, Proc. of Symposium on Parallel Processing JSPP '94 pp. 129-136 (1994).
Information Processing Society of Japan, IPSJ SIG Notes ARC, vol. 92, No.64 pp. 89-96 (1992).
"Virtual-Channel Flow Control", William J. Dally, IEEE Transactions on Parallel and Distributed Systems, vol. 3, No.2 (1992).
Tanaka Teruo
Yasuda Yoshiko
Dung Dinh C.
Hitachi , Ltd.
LandOfFree
Parallel computer system using properties of messages to route t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel computer system using properties of messages to route t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel computer system using properties of messages to route t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1379543