Hardware implemented multiplier

Details Hardware implemented multiplier Hardware implemented multiplier

1993-12-22

1995-12-05

Envall, Jr., Roy N.

Boots, shoes, and leggings

364754, 364760, G06F 752

Patent

active

054735599

ABSTRACT:
A sign inverting Booth encoder included in an encoding circuit generates a control signal designating a partial product having a sign different from that designated by an output signal generated from a conventional Booth encoder. A partial product generating circuit generates a partial product according to the control signal from the encoding circuit. A partial product having a sign inverted or non-inverted is generated from a shifter/inverter circuit. A converting circuit generates three-value redundant binary numbers using a sign inverted partial product and a sign non-inverted partial product as a set. An intermediate sum generating circuit performs a redundant binary addition of the three-value redundant binary numbers to generate a final redundant binary number. A final adding circuit converts the finally generated three-value redundant binary number into an ordinary binary number to generate a product Z of binary numbers X and Y. As a result, a multiplier performing multiplication at a high speed with a smaller number of elements is implemented.

REFERENCES:
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 4890127 (1989-12-01), Darley
"High-Speed VLSI Multiplication Algorithm With a Redundant Binary Addition Tree", IEEE Transactions on Computers, vol. 34, No. 9, Sep. 1985, Takagi et al., pp. 789-796.
"A VLSI-Oriented High-Speed Multiplier Using a Redundant Binary Addition Tree", Systems Computers Controls, vol. 14, No. 4, 1983, Takagi et al., pp. 19-28.
"A Fast Multi-Valued SBNR Multiplier", Brain Arnold et al., pp. 738-742.
"A Fast VLSI Adder Architecture", IEEE Journal of Solid-State Circuits, May 1992, No. 5, H. R. Srinivas et al., pp. 761-767.
European Search Report.
"A Suggestion for a Fast Multiplier", by C. S. Wallace, IEEE Trans. Electron. Comput. EC-13:14017.
"A 10-NS 54.times.54-B Parallel Structured Full Array Multiplier with 0.5-um CMOS Technology", by J. Mori et al., IEE Journal of Solid-State Circuits.
"200 MHz 16-Bit BiCMOS Signal Processor", by M. Yamashina et al., IEEE International Solid-State Circuits Conference.
"High-Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor", by Shigeo Kuniobu et al., IEICE Trans., Electron.

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