Device for the protection of an integrated circuit against power

Details Device for the protection of an integrated circuit against power Device for the protection of an integrated circuit against power

1993-08-02

1995-12-05

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Voltage regulator protective circuits

361 56, 361 58, 361 92, 3642734, 3643466, G06F 128, G06F 130, H02H 900

Patent

active

054734967

ABSTRACT:
A circuit for protecting nonvolatile memories against loss of Vcc while Vpp is high. An NMOS gated by Vcc is connected, in series with a load element, between Vpp and ground. The node between the NMOS and the load element gates a PMOS which is interposed between Vpp and the memory. Thus when Vcc fails while Vpp is high, the NMOS will turn off, and the load element will pull up the gate of the PMOS to turn it off, interrupting the Vpp supply. This prevents spurious write or erase operations under these circumstances. The circuit can be designed to trigger at threshold voltages as low as V.sub.TN, and is thus particularly advantageous for operation with specified Vcc values of 3 Volts or less.

REFERENCES:
patent: 3624617 (1971-11-01), Putterman
patent: 4096560 (1978-06-01), Footh
patent: 4975883 (1990-12-01), Baker et al.

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