Method and apparatus for optimizing dependent operand flow withi

Boots – shoes – and leggings

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36476005, 395562, G06F 752

Patent

active

058926992

ABSTRACT:
A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

REFERENCES:
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patent: 5638313 (1997-06-01), Chu
patent: 5748934 (1998-05-01), Lesartre et al.
patent: 5751619 (1998-05-01), Agarwal et al.
A Signed Binary Multiplication Technique, by Andrew D. Booth, Q.J. Mech. Appl. Math. 4:236-240 (1951).

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