Method of forming isolation regions in a semiconductor device

Details Method of forming isolation regions in a semiconductor device Method of forming isolation regions in a semiconductor device

1986-06-25

1987-09-15

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 67, H01L 21425, H01L 21473

Patent

active

046929924

ABSTRACT:
A method of forming a semiconductor device is disclosed wherein the doping concentration of the side wall of a trench isolation region is increased. An opening is formed in a first masking layer so as to expose a portion of the semiconductor substrate. Then, dopants are introduced through the opening in the masking layer so as to form a heavily doped region within the semiconductor substrate. An isolation trench is then formed in the exposed portion of the semiconductor substrate. At least a portion of the side wall of the trench is located in the heavily doped region. The heavily doped region increases the threshold voltage of the side wall transistor and thereby reduces the leakage current along the side wall of the trench isolation region.

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"Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages," 1985 Symposium on VLSI Technology, Digest of Technical Papers, Japanese Society of Applied Physics, May 14-16, 1985, Kobe, Japan, pp. 58-59.

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