Ring systolic array system for synchronously performing matrix/n

Details Ring systolic array system for synchronously performing matrix/n Ring systolic array system for synchronously performing matrix/n

1991-12-11

1995-12-26

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364964, 3649642, 36496421, 395490, 395468, G06F 1208

Patent

active

054796253

ABSTRACT:
A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned microcomputer system), which is accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) which is accessible by the central processing system is performed. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address does not correspond to that area accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.

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