System for combining and encoding first plurality of video signa

Details System for combining and encoding first plurality of video signa System for combining and encoding first plurality of video signa

1992-06-05

1995-12-26

Lee, Thomas C.

Boots, shoes, and leggings

395500, 39520001, 36424233, 36493544, 36493546, 36493141, 3649445, 341143, G06F 1300, G06F 1314, G06F 700, G06F 714

Patent

active

054796172

ABSTRACT:
A type 286, 386, or 486 Personal Computer having a host controller comprising a standard VGA controller, a microprocessor, a receive and transmit unit, and an encoder is coupled via a ten line telephone cable to a remote VGA color display workstation having a base unit comprising a decoder, a RAMDAC, and microprocessor, and a receive and transmit unit. The encoder intelligently combines ten video signals (a pixel clock, six pixel signals, a video blanking interval (VBI) signal, and vertical and horizontal sync signals) and an I/O data transmit signal into four signals which are transmitted in a balanced fashion (requiring eight lines) to minimize signal noise so that shielding is unnecessary. An additional line is used to provide a ground reference to the remote workstation, and another line is used to provide an I/O data receive signal to the host controller microprocessor. The base unit decoder decodes the balanced signals to provide the I/O transmit signal to the base unit microprocessor, the vertical and horizontal sync signals to the remote workstation VGA monitor, and the VBI and pixel signals to the base unit RAMDAC. Remaining signals required by the base unit RAMDAC are provided by the base unit microprocessor.

REFERENCES:
patent: 3832483 (1974-08-01), Jirka
patent: 3967074 (1976-06-01), Schillo
patent: 4797750 (1989-01-01), Karweit
patent: 4901342 (1990-02-01), Jones
patent: 4980897 (1990-12-01), Decker et al.
patent: 5235680 (1993-08-01), Bijnagte
"Combined Correlatively Encoded/Multi-h CPFSK Signalling", Fonseka et al., IEEEE, 1991, pp. 797-801.

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