Circuit design conversion apparatus

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Details

364489, 364488, 371 223, G06F 1560

Patent

active

050670913

ABSTRACT:
A circuit design conversion apparatus comprises hierarchical circuit data memory, hierarchical structure analyzer, hierarchical structure data memory, conversion module register, conversion rule memory, conversion module table memory, conversion control unit, module pick-up unit, circuit design conversion unit and conversion rule remake unit. Circuit connection data which hierarchically described the connection of an LSI is input to the hierarchial circuit data memory. Hierarchical structure analyzer analyzes the circuit structure to obtain a hierarchical structure data, which in turn is stored in the hierarchical structure data memory. The name of a module, to be scan designed, is initially registered in the conversion rule memory. Considering the hierarchical structure data and the conversion rule the name of a module higher in level than the module registered in the conversion rule is registered in conversion module table memory which includes a pointer for representing a modules to be scan designed next. Conversion control unit supplies, to module pick-up unit, the name of a module which is pointed by a pointer. Module pick-up unit picks up circuit connection data, relating to that module, from the hierarchical circuit data memory, and supplies it to circuit design conversion unit to convert into a scan design relating to that module.

REFERENCES:
patent: 4691161 (1987-09-01), Kant et al.
patent: 4803636 (1989-02-01), Nishiyama et al.
"A Logic Design Structure for LSI Testability", by Eichelberger et al., IEEE 1977, pp. 206-212.
Proceedings Custom Integrated Circuits Conference, pp. 195-163, "Automation in Design for Testability"; Agrawal et al., May 1984.
Aida Corporation Catalog, "Scan Ring Generation Program-Scangen--", John J. Zasio; 1987.
Computer Design, "Testability System Reduces Scan Path Penalty"; Richard Goering; Aug. 15, 1986.

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