Excavating
Patent
1987-01-21
1989-02-28
Fleming, Michael R.
Excavating
371 40, G06F 1110
Patent
active
048092754
ABSTRACT:
A parity generating circuit comprises first and second dividing circuits and an output circuit. Each element of a row matrix W.sub.0 ' described by W.sub.0 '=[D.sub.1, D.sub.2, . . . , D.sub.i, O, . . . O, D.sub.j, . . . , D.sub.n ] in which (n-k) m-bit parities P.sub.i+1 through P.sub.j-1 of a row matrix W.sub.0 described by W.sub.0 =[D.sub.1, D.sub.2, . . . , D.sub.i, P.sub.i+1, . . . , P.sub.j-1, D.sub.j, . . . , D.sub.n ] and describing a Reed Solomon code are zero vectors is applied to an input terminal and is supplied to the first dividing circuit wherein dividing steps are carried out, where D.sub.1 through D.sub.i and D.sub.j through D.sub.n denote k m-bit data and n-k=j-i-1, 2.sup.m -1.gtoreq.n and n>j>i. The second dividing circuit uses divided results from the first dividing circuit as initial values and carries out dividing steps with the input elements made "0". The output circuit outputs (n-k) divided results from the second dividing circuit as the parities P.sub.i+1 through P.sub.-1.
REFERENCES:
patent: 4583223 (1986-04-01), Yamada
patent: 4627058 (1986-12-01), Moriyama
patent: 4646301 (1987-02-01), Okamoto
patent: 4646303 (1987-02-01), Narusawa
patent: 4675869 (1987-06-01), Driessen
"Error Correcting Codes" W. W. Peterson & E. J. Weldon.
Blahut, Richard E., "Theory and Practice of Error Control Codes", Addison-Wesley, 1983, pp. 96-100.
Inoue Yasuo
Yamada Yasuhiro
Fleming Michael R.
Victor Company of Japan Ltd.
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