Dual-port timing controller

Details Dual-port timing controller Dual-port timing controller

1987-04-02

1989-02-28

Griffin, Robert L.

Multiplex communications

Wide area network

Packet switching

H04J 324

Patent

active

048092690

ABSTRACT:
A dual port timing controller (DPTC) (56) in conjunction with an interprocessor communication register (596) provides a shared random access memory (S-RAM)(22a). The S-RAM can be accessed either by a local processor (18) or a host processor (595) which, in a preferred configuration, controls an integrated circuit integrated services data protocol controller. The DPTC provides control signals allowing an ordinary RAM to be operated as an S-RAM. The DPTC includes a semaphore register (596) that stores bidirectional interprocessor interrupts, enabling passing of high level messages between the local and host processors.

REFERENCES:
patent: 4290133 (1981-09-01), Stewart et al.
patent: 4530093 (1985-07-01), Akram et al.
patent: 4637015 (1987-01-01), Bobey
patent: 4692918 (1987-09-01), Elliot et al.

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