Excavating
Patent
1994-03-10
1995-12-26
Beausoliel, Jr., Robert W.
Excavating
371 221, G06F 1100
Patent
active
054794153
ABSTRACT:
A circuit for generating product-specific digital test signals for testing memories, etc., the test signals comprising a test pulse occurring during a pulse interval and generated from predetermined data and timing signals. A format memory (7-11) stores addressable test signal formats (in the form of digital values denoting the test signals curve unrelated to time) for each data signal. These digital values are read out time parallel to each other and are combined by a flip-flop circuit (7-24) in the order of their occurrence during the pulse interval with timing signals for the respective data signal to form a control signal. The internal signal delay of the flip-flop circuit determining the generation of the test signals is invariably of the same value. This circuit may not only be used for test purposes but also generally for computer control, in particular for addressing main memories and buffers.
REFERENCES:
patent: 3772595 (1973-11-01), De Wolf et al.
patent: 4013951 (1977-03-01), Ezoe et al.
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 4389614 (1983-06-01), Staiger
patent: 4402081 (1983-08-01), Ichmiya et al.
patent: 4450560 (1984-05-01), Conner
patent: 4802168 (1989-01-01), Yamanoi et al.
patent: 4855681 (1989-08-01), Millham
patent: 4998025 (1991-03-01), Watanabe
Beausoliel, Jr. Robert W.
Chung Phung My
International Business Machines - Corporation
Leas James M.
LandOfFree
Method and apparatus for generating test pulses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for generating test pulses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating test pulses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1374408