Fishing – trapping – and vermin destroying
Patent
1994-11-07
1995-12-05
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437190, 437192, H01L 21441
Patent
active
054729122
ABSTRACT:
A conductive layer is formed over an insulating layer and extending down into a contact opening. An insulating layer is then deposited over the device and in the opening, and etched back to form a plug of dielectric material in the bottom of the opening. An aluminum layer is then deposited over the device and in the opening under such conditions as to cause a substantially complete fill of the opening by the aluminum, and result in a planar surface above the opening.
REFERENCES:
patent: 3158504 (1964-11-01), Anderson
patent: 3900598 (1975-08-01), Hall et al.
patent: 4107726 (1978-08-01), Schilling
patent: 4436582 (1984-03-01), Saxena
patent: 4502209 (1985-03-01), Eizenberg et al.
patent: 4566177 (1986-01-01), van de Ven
patent: 4592802 (1986-06-01), Deleonibus et al.
patent: 4661228 (1987-04-01), Mintz
patent: 4756810 (1988-07-01), Lamont et al.
patent: 4758533 (1988-07-01), Magee et al.
patent: 4772571 (1988-09-01), Scovell et al.
patent: 4833519 (1989-05-01), Kawano et al.
patent: 4837183 (1989-06-01), Polito et al.
patent: 4892844 (1990-01-01), Cheung
patent: 4944961 (1990-07-01), Lu
patent: 4970176 (1990-11-01), Tracy et al.
patent: 4975389 (1990-12-01), Ryan et al.
patent: 4976839 (1990-12-01), Inoue
patent: 4988423 (1991-01-01), Yamamoto
patent: 4994162 (1991-02-01), Armstrong
patent: 5106781 (1992-04-01), De Vries
patent: 5108570 (1992-04-01), Wang
patent: 5108951 (1992-04-01), Chen et al.
patent: 5231055 (1993-07-01), Smith
patent: 5312772 (1994-05-01), Yokoyama et al.
TiN Metallization Barriers: from 1.2.mu. to 0.35.mu. Technology Fabio Pintchovski and Ed Travis, Motorola, Inc., Austin, Tex. pp. 777-786, 1992 Materials Research Society.
Development of a Planarized Al-S1 Contact Filling Technology Hisako Ono, et al., VMIC Conference, Jun. 1990, pp. 76-82.
Aluminum Metallization for ULSI, Dipankar Pramanik et al., Solid State Technology Mar. 1990, No. 3, Westford, Mass. pp. 73-79.
Thin-film reactions of Al with Co, Cr, Mo, Ta, Ti, and W E. G. Golgan, et al., vol. 4, No. 4, 1989 Materials Research Society, pp. 815-820.
Planarized Aluminum Deposition on TiW and TiN Layers by High Temperature Evaporation, G. E. Georgiou, et al., AT&T Bell Laboratories, Jun. 1989 VMIC Conference, pp. 315-321.
The properties of aluminum thin films sputter deposited at elevated temperatures, M. Inoue et al., J. Vac. Sci. Technol. May 6, 1988, pp. 1636-1939.
Evaluation of Titanium as a Diffusion Barrier Between Aluminum and Silicon for 1.2 .mu.m CMOS Integrated Circuits, M. Farahani, et al., Electrochemical Society Active Member, pp. 2835-2845, Nov. 1987.
Nonconformal Al Via Filling and Planarization by Partially Ionized Beam Deposition for Multilevel Interconnection, S. N. Mei, et al., Oct. 1987 IEEE Electron Devices Letters, pp. 503-505.
Aluminum Alloy Planarization for Topography Control of Multilevel VLSI Interconnect, van Gogh, et al., Jun. 1987, V-MIC Conf., IEEE, pp. 371-375.
Interconnect Materials for VLSI Circuits, Y. Pauleau, Centre National d'Etudes des Telecommunications, Meylan, France Apr. 1987, Solid State Technology, pp. 155-162.
"Planarization of Al Alloy Film During High Rate Sputtering", V. Hoffman, et al., Intl. Conf. on Metallurgical Coatings, San Diego, Mar. 1986, Report No. 122, pp. 1-20.
"Sputtering and Interconnect Trends, Peter Burggraaf, Semiconductor International", Nov. 1984, pp. 70-73.
"TiN formed by evaporation as a diffusion barrier between Al and Si", C. Y. Ting, IBM T. J. Watson Research Center, Yorktown Heights, N.Y. 10598, May 6, 1982, J. Vac. Sci. Tech. pp. 14-18.
"High-temperature contact structures for silicon semiconductor devices", M. Wittmer, Brown Boveri Research Center, 5405 Baden-Dattwil, Switzerland, Appl. Phys. Lett., Sep. 1980 pp. 540-542.
"Silicon Processing for the VLSI Era", S. Wolf, et al., Lattice Press, Inc., 1986, pp. 332-374.
Chaudhari Chandra
Hill Kenneth C.
Jorgenson Lisa K.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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