Semiconductor memory device having a plurality of blocks

Details Semiconductor memory device having a plurality of blocks Semiconductor memory device having a plurality of blocks

1994-06-17

1995-12-26

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365154, 365156, 365190, 36518904, G11C 800, G11C 700

Patent

active

054793734

ABSTRACT:
A semiconductor memory device comprises: a memory cell array having memory cells (1) arranged into a matrix pattern; a plurality of word lines (WL) each for selecting the memory cells arranged in the same line of the memory cell array; a plurality of bit lines (BL, NBL) each connected in common to the memory cells arranged in the same column of the memory cell array, for transmitting and receiving data to and from one of the memory cells selected by one of the word lines; a plurality of first column decoders (FCD) each for selectively connecting one of a predetermined number of the bit lines to one of a plurality of first common data lines (FDL, FNDL); a plurality of writing transistors (2) each provided for one of a plurality of the first common data lines and each having a data input line for inputting data applied from the outside thereto, the data inputted from the outside through the data input line being written in one of the selected memory cells so that data of a plurality of bits can be simultaneously written; a second column decoder (SCD) for selectively connecting one of the first common data lines to a second common data line; and a sense amplifier (4) connected to the second common data line, for reading data from the selected memory cell via the bit line, the first common data line and the second common data line, and for outputting the read data to the outside as one-bit data.

REFERENCES:
patent: 5285414 (1994-02-01), Yamauchi et al.
patent: 5305264 (1994-04-01), Takahashi
patent: 5357479 (1994-10-01), Matsui

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