1990-08-15
1991-11-19
James, Andrew J.
357 80, H01L 2302
Patent
active
050670069
ABSTRACT:
The device includes an insulating substrate and first and second conducting patterns, electrically insulated from another, formed on the substrate. The second conducting pattern is connected to ground. A semiconductor chip is die-bonded to the first conducting pattern. The chip has a reception circuit, including a capacitor, formed therein, and a metal film is formed on a back surface of the chip. The capacitor includes a first terminal and a second terminal, with one of the first terminal and the second terminal being electrically connected to the first conducting pattern, such that the electric potential of the capacitor is transmitted to the metal film formed on the back surface of the chip. A buffer amplifier is interposed between the one of the first terminal and the second terminal which is electrically connected to the first conducting pattern such that the potential of the capacitor is transmitted to the metal film through the buffer amplifier. The first and second terminals constitute parallel electrode patterns forming the capacitor.
REFERENCES:
patent: 4266239 (1981-05-01), Miyagaki et al.
patent: 4617586 (1986-10-01), Cuvilliers et al.
patent: 4788584 (1988-11-01), Hirano et al.
patent: 4952795 (1990-08-01), Gauthier et al.
Davenport T.
James Andrew J.
Sumitomo Electric Industries Ltd.
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