Computer-aided method of designing a carry-lookahead adder

Details Computer-aided method of designing a carry-lookahead adder Computer-aided method of designing a carry-lookahead adder

1993-03-15

1995-12-26

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364578, 364787, G06F 750

Patent

active

054793564

ABSTRACT:
Using a computer-aided method to design carry-lookahead adders to add two binary numbers and an input carry bit. In the first preferred embodiment, a length-number and a blocks-in-group number are entered into the computer by a user. The computer, responding to the length-number automatically designs a first structure with a plurality of logic blocks. Using the blocks-in-group number entered, the computer designs a second structure specifying the number of preceding-level logic blocks to be grouped into next-level logic blocks. Then, the computer automatically designs one or more next-level logic blocks. The first structure receives the binary numbers and produces the propagate and the generate bit. The logic blocks in the second structure receive bits from preceding-level logic blocks and operate on bits in parallel to produce the output carry bit of the adder. Based on the few numbers entered, the computer formulates the logic circuits to produce the output-carry bit and the sum bits of the adder. In a second preferred embodiment, the output-carry bit is formed with some rippling of the carry bit from one block to the next.

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John P. Fishburn, "A Depth-Decreasing Heuristic for Combinational Logic or How to Convert a Ripple-Carry Adder into a Carry-Lookahead Adder or Anything In-Between", 27th ACM/IEEE Design Automation Conference, 1990, pp. 361-364.
Mekhallalati et al., "New Parallel Multiplier Design", Electronics Letters, 13th Aug. 1992, vol. 28, No. 17, pp. 1650-1651.
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Pak K. Chan et al., "Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming", IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 920-930.

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