Programmable logic array with reduced power consumption

Details Programmable logic array with reduced power consumption Programmable logic array with reduced power consumption

1989-04-06

1991-07-16

Shaw, Dale M.

Boots, shoes, and leggings

G06F 738

Patent

active

050330179

ABSTRACT:
A programmable logic array includes a programmable logic array being precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.

REFERENCES:
patent: 3896418 (1975-07-01), Brown
patent: 4262352 (1981-04-01), Kobayashi et al.
patent: 4317180 (1982-02-01), Lies
patent: 4721868 (1988-01-01), Cornell et al.
patent: 4812685 (1989-03-01), Anceau
patent: 4831285 (1989-05-01), Gaiser
patent: 4839539 (1989-06-01), Takata et al.

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