Solid state imager having a signal processing circuit for reduci

Details Solid state imager having a signal processing circuit for reduci Solid state imager having a signal processing circuit for reduci

1987-06-16

1989-02-28

Groody, James J.

Facsimile and static presentation processing

Facsimile

Recording apparatus

35821318, 35811331, H04N 5335

Patent

active

048090743

ABSTRACT:
The read out of a signal from an imaging device is conducted during a voltage read out mode, and resetting of a signal output line is carried out each time a signal of a plurality of pixels is read out. Signal charge is accumulated on the signal output line, and is then read out. The accumulated signal is differenced or differentiated at a later stage to reproduce an original signal.

REFERENCES:
patent: 4333111 (1982-06-01), Noda et al.
patent: 4335406 (1982-06-01), Ohba et al.
patent: 4355335 (1982-10-01), Imaide et al.
"Institute of Television Engineers of Japan Technical Report" (TEBS 109-3), vol. 9, No. 45, ED 938 (Feb. 1986).
"A Solid State Camera with a Horizontal Readout MOS Imager", IEEE Transactions on Consumer Electronics, Noda et al., vol. CE-3d, No. 3, (Aug. 1986).

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