Pulse or digital communications – Repeaters – Testing
Patent
1985-10-17
1989-02-14
Griffin, Robert L.
Pulse or digital communications
Repeaters
Testing
375121, 370 91, H03K 900
Patent
active
048051942
ABSTRACT:
A serial data communication system including a microprocessor and an asynchronous communication interface adapter (ACIA) implementing a SMPTE Supervisory Protocol for Digital Interface Control. The system detects the beginning of a break character as the first framing error which occurs after the last word of a data block has been detected. The receive clock of the ACIA is disabled in response to the start of break detection by the software reset of a bistable device which disables a receive clock gate. The framing error detection circuit of the ACIA is additionally disabled by the termination of the receive clock signal. The end of the break character is detected as the space to mark transition before the start of the first word in the data block. The receive clock is enabled by setting the bistable device with the end of break transition thereby detecting the termination of the break character and enabling the receive clock gate. This operation correctly restarts the frame timing circuit of the ACIA at the start bit of the first word of a data block.
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SMPTE Recommended Practice, RP 113, "Supervisory Protocol for Digital Control Interface".
Proposed American National Standard, ANSI PH22.207M, "Electrical and Mechanical Characteristics for Digital Control Interface".
Ampex Corporation
Chin Stephen
Griffin Robert L.
LaBarre James A.
Lange Richard P.
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