Boots – shoes – and leggings
Patent
1987-05-11
1989-08-01
Shaw, Gareth D.
Boots, shoes, and leggings
364938, G06F 900
Patent
active
048538892
ABSTRACT:
Arrangement and method for avoiding the processing time associated with executing branch instructions in a computer. An instruction fetch unit appends a next instruction address field to each instruction it passes it via an instruction cache to an instruction execution unit. The fetch unit decodes the present instruction being read and the next sequential instruction in main memory. If neither instruction is a branch instruction, the next address field is set to the address of the next sequential instruction. If the present instruction is a branch, the next instruction address field is set to the branch address contained in the present instruction. If neither of these cases are true and the next sequential instruction from main memory is a branch, the next instruction address field is set to the branch address of this instruction. The execution unit uses the next instruction address to access instructions from the instruction cache. Thus, execution of branch instructions by the execution unit are avoided.
REFERENCES:
"The Architecture of High Performance Computers", by Roland N. Ibbett, Reader in Computer Science, Univ. of Manchester, Springer-Verlag New York Inc.
"A Processor for a High-Performance Personal Computer", by B. W. Lampson and K. A. Pier, XEROX Palo Alto Research Center, Palo Alto, CA 94304.
"An Instruction Fetch Unit for a High-Performance Personal Computer", by B. W. Lampson, G. A. McDaniel and S. M. Ornstein, XEROX Palo Alto Research Center, Palo Alto, CA 94304.
Ditzel David R.
McLellan, Jr. Hubert R.
American Telephone and Telegraph Company AT&T Bell Laboratories
Herndon Jerry W.
Mills John G.
Nimtz Robert O.
Shaw Gareth D.
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