Implant method for advanced stacked capacitors

Fishing – trapping – and vermin destroying

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437 46, 437 47, 437 60, 437191, 437919, H01L 2170

Patent

active

050666061

ABSTRACT:
An implant method to develop a storage node access MOSFET to a 3-dimensional stacked capacitor storage cell during a semiconductor fabrication process. This implant method utilizes one layer of oxide to serve as both a MOSFET's (N-channel or P-channel) lightly doped drain spacer as well as a subsequent polysilicon etch stopper when etching a FET's digitline. As DRAM density increases the use of only one oxide layer decreases oxide bridging or buildup.

REFERENCES:
patent: 4935380 (1990-06-01), Okumura
patent: 4992389 (1991-02-01), Ogura et al.

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