Fishing – trapping – and vermin destroying
Patent
1994-06-03
1995-12-26
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 12, 437 61, 148DIG50, H01L 21306
Patent
active
054787580
ABSTRACT:
A method of making a gettering structure for dielectrically isolated wafer structures, such as bonded wafers. A getterer layer is deposited over the wafer having semiconductor regions isolated from each other by trenches. The polysilicon is etched back leaving the polysilicon on the sides of the regions. The polysilicon may be doped. The polysilicon is oxidized and a second layer of polysilicon may be deposited to fill voids in the trenches.
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Wolf et al., vol. I, Silicon Processing For the VLSI Era, Lattice Press, 1986.
AT&T Corp.
Gurley Lynne A.
Hearn Brian E.
McLellan Scott W.
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