Pipelined computer with half machine cycle alternating write con

Details Pipelined computer with half machine cycle alternating write con Pipelined computer with half machine cycle alternating write con

1994-05-05

1995-12-12

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642318, 364270, 3642704, 3642705, 364271, 3642716, G06F 938

Patent

active

054758556

ABSTRACT:
In a data processing system, arithmetic/logic units, each with a different number stages, are pipelined for executing arithmetic/logic instructions stored in main memory in full machine cycles. One of the outputs of the arithmetic/logic units is selected. In response to a memory access instruction, data is fetched from the main memory and stored into general registers in which the results of instruction execution from the arithmetic/logic units are also stored. A selector has a first input terminal which receives the selected output of the arithmetic/logic units, a second input terminal for receiving the fetched data, and an output terminal coupled to the general registers. In response to half machine clock pulses, the selector alternately establishes a first path between the first input terminal and the output terminal and a second path between the second input terminal and the output terminal during mutually exclusive times of half machine cycle.

REFERENCES:
patent: 4639866 (1987-01-01), Loo
patent: 4745302 (1988-05-01), Hanawa et al.
patent: 5001626 (1991-03-01), Kashiyama et al.
patent: 5023828 (1991-06-01), Grundmann et al.
patent: 5115393 (1992-05-01), Kashiyama et al.
patent: 5167025 (1992-11-01), Kusakabe

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