Boots – shoes – and leggings
Patent
1989-09-22
1991-07-16
Heckler, Thomas M.
Boots, shoes, and leggings
3642401, 364258, 3642552, 3642592, 3642543, G06F 1206
Patent
active
050329863
ABSTRACT:
A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/subtractor in the auxiliary arithmetic logic units either adds or substracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register. The pair of auxiliary arithmetic logic units are operable in parallel with each other, and in parallel with the primary arithmetic logic unit. The two memory addresses are presented to the on-chip memory in time-multiplexed fashion, so that two memory accesses may be performed in a single machine cycle.
REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 4074351 (1978-02-01), Boone et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4217657 (1980-08-01), Handley et al.
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4598266 (1986-07-01), Bernardson
patent: 4713748 (1987-12-01), Magar et al.
patent: 4722067 (1988-01-01), Williams
patent: 4742479 (1988-05-01), Kloker et al.
patent: 4800486 (1989-01-01), Horst et al.
patent: 4912636 (1990-03-01), Magar et al.
Electronic Letters, 5th Jun. 1980, vol. 16, No. 12, "Practical Realisation of mod p, p Prime Multiplier" by A. S. Ramnarayan, pp. 466-467.
J. van Meerbergen et al., "An 8MIPs CMOS Digital Signal Processor" IEEE International Solid-State Circuits Conference, 1986, pp. 84-85, 315-316.
J. Laborie et al., "VLSI Digital Signal Processor (PSI)", ICASSP 86, IEEE, 1986, pp. 389-392.
"UPD77230 Advanced Signal Processor", NEC Electronics Inc., 1986, pp. 1-15.
"DSP56001: 56-Bit General Purpose Digital Signal Processor", Motorola, 1986, pp. 1-25.
Y. Mochida et al., "A High Performance LSI Digital Signal Processor for Communication", IEEE Journal on Selected Areas in Communications, vol. SAC, No. 2, Mar. 1985, pp. 347-356.
H. Yamauchi et al., "An 18-Bit Floating-Point Signal Processor VLSI with an On-Chip 512W Dual-Port RAM", IEEE, 1985, pp. 204-207.
Y. Kawakami et al., "A 32-Bit Floating Point CMOS Digital Signal Processor", 1986, pp. 86-87.
Marshall Steven P.
Pathak Bimal
Potts James F.
Demond Thomas W.
Heckler Thomas M.
Hollander James F.
Sharp Melvin
Texas Instruments Incorporated
LandOfFree
Data processing device with parallel circular addressing hardwar does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing device with parallel circular addressing hardwar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing device with parallel circular addressing hardwar will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-136762